1. Field of the Invention
The present invention relates to a display apparatus and a camera, and particularly to control of a sampling unit and arrangement of data lines for preventing the degrading of image quality in the display apparatus.
2. Description of the Related Art
An active matrix type display apparatus using an organic electroluminescence element (hereafter, referred to as an organic EL element) and a liquid crystal element, etc. has a display element and a circuit for controlling the display status of the element for each pixel circuit. A transistor which makes up a pixel circuit is made up of an amorphous silicon thin-film transistor (TFT) and a polysilicon TFT, etc. Pixel circuits are selected in units of lines by a scanning line which connects pixel circuits in a row direction of a matrix, and receive image signals from a data line extending in a column direction. The image signal is generated at a data line driving circuit.
The data line driving circuits may be made up of TFTs and provided in each column of the data lines along one side of a pixel circuit matrix. Moreover, the image signal may be created at an integrated circuit connected to a display panel and transmitted to the data line through a wiring (hereafter, referred to as an image signal line) provided in the display panel.
In the latter case, if image signals of the number of data lines (that is, the number of columns of a matrix) are generated at an integrated circuit to be fed to a display panel, a large number of image signal lines needs to be arranged on the display panel. As a result, the area occupied by the image signal lines will cause an increase in the size of a so-called frame edge portion of a display panel. For that reason, a configuration has been developed in which the number of wirings is reduced by decreasing the number of outputs of the integrated circuit to be less than the number of data lines so that image signals are fed from one output to a plurality of data lines in a time division manner.
Japanese Patent Application Laid-Open No. 562-055625 proposes a circuit which connects an image signal line and a data line with a TFT switch. When the data lines are 640 and the signal lines are 8, the 640 TFT switches provided corresponding to each data line are at one end connected to a data line and, at the other end, to an image signal line at a rate of one for every 8 columns. Eight TFT switches are concurrently opened/closed by a control signal of one control line.
Image signals of the data lines of 80 columns are fed in time series to one image signal line and are successively sampled by TFT switches at data lines of 80 columns. The sampled image signals are retained in a parasitic capacitor of a data line or a holding capacitor of a pixel circuit selected by a selection signal of a scanning line.
In such a configuration that an image signal line and a data line are connected by a TFT switch, image signals of every 8 columns are concurrently fed to the data line by TFT switches which are concurrently opened/closed. That is, image signals will be successively sampled block by block, with one block including 8 columns.
In this case, Japanese Patent Application Laid-Open No. S61-180293 points out that an unintended image boundary appears at the boundary between the data lines which receive image data at different timings resulting in a degrading of image quality. This is because the pixel circuit which receives and retains an image signal from a data line is subjected to voltage variation caused by the data line of the next column which receives image signals thereafter. Japanese Patent Application Laid-Open No. S61-180293 solves the above described problem by adding the varying part of the voltage to an image signal before generating it.
By the way, in an active matrix type display apparatus using an organic EL, PCT International Publication No. WO98/036407 proposes a layout method in which a power source line is shared by adjacent pixel circuits to increase the pixel density. By arranging pixel circuits in both sides of a power source line extending in a column direction and commonly supplying power to the pixel circuits of the two columns, the number of power source lines can be decreased to reduce the spacing between the pixel circuits. In two adjoining pixel circuits aligning in the row direction, circuit elements such as transistors, capacitors, and wirings are arranged in line symmetry with respect to an axis in the column direction (hereafter, which is referred to as a flip arrangement). The data line is arranged opposite the power source line with respect to the pixel circuit. Therefore, between adjacent pixel-circuit columns, two data lines and a power source line are alternately arranged.
A new problem will arise when applying the above described configuration, in which image signal lines and data lines are connected by TFT switches, to an active matrix display apparatus in which the pixel circuits are provided in a flip arrangement.
That is, when a boundary of data lines in which image signals are sampled at different timings is placed between two data lines which are arranged between pixel circuits in flip arrangement, the data line which first receives and retains an image signal will be seriously affected by the voltage variation of the adjacent data line. In contrast, when a boundary of data lines in which image signals are sampled at different timings is placed between the data lines which are spaced apart with two columns of pixel circuits interposed therebetween, there is little influence of the voltage variation of an adjacent data line.
Thus, when data lines are arranged in groups of two, the magnitude of parasitic capacity between the data lines alternately varies resulting in that two types of boundaries with and without a large effect of voltage variation are created as the boundary between pixel-circuit columns of different sampling timings. For that reason, image signals need to be corrected by respectively different methods for every two boundaries requiring a correction circuit therefor.